Field of the Disclosure
The present disclosure generally relates to processors and more particularly to techniques for scheduling execution of operations at a processor.
Description of the Related Art
Some processors employ an instruction pipeline to facilitate execution of instructions. The instruction pipeline typically includes a fetch stage to fetch instructions in a program stream, a decode stage to decode each instruction into one or more operations, a dispatch stage to dispatch the decoded operations to one or more execution units, and a retire stage to retire instructions after their corresponding operations have been executed. Each operation requires a corresponding number of resources in order to be executed at the execution units. For example, a load/store operation (an operation to retrieve data from or store data to memory) can require one or more registers in a physical register file, space in a load/store queue of a load/store unit, and the like. The dispatch stage of the instruction pipeline holds each operation in a queue until the resources to execute the operation are available (i.e. not being used to execute other operations). However, because operations behind the held operation in the program stream are also held at the dispatch stage, an operation that awaits resources for a relatively long period of time can significantly reduce processor performance.
The use of the same reference symbols in different drawings indicates similar or identical items.